**** SRAM Testing

.lib "/net/plato.ee.Virginia.EDU/users/ab9ca/Research/HSPICE/V1.8.0.3DM/HSPICE/models/allModels.inc" sf
.inc "/net/plato.ee.Virginia.EDU/users/ab9ca/Research/HSPICE/V1.8.0.3DM/HSPICE/models/hspice_fixed_corner.param"
.inc "/net/plato.ee.Virginia.EDU/users/ab9ca/Research/HSPICE/SRAM_TEST/DataMemSims/DATA_MEM.sp"
.inc "./SRAM_Deck_0.5v.vec_us.stimulus"
.inc "HSIM.inc"
.inc "Probe.inc"
.inc "Meas.inc"
*.inc "SRAM.prn.inc"
.param VDD=0.5
.param Num=1
VVDDUS VDD  VSS VDD
VVDDA  VDDP VDD 0v
VVDDP  VDDA VDD 0v
VVSS   VSS  0   0v
.temp 27c
.ic v(XI0.XI*.XI*.XIcell*.net075) = VDD




.meas tran tcyc_1 when v(CLK)='VDD*0.1' td=0us rise=1
.meas tran tcyc_2 when v(CLK)='VDD*0.1' td=0us rise=2
.meas tran tcyc_3 when v(CLK)='VDD*0.1' td=0us rise=3
.meas tran tcyc_4 when v(CLK)='VDD*0.1' td=0us rise=4
.meas tran tcyc_5 when v(CLK)='VDD*0.1' td=0us rise=5

.meas tran IAvg_Write_1 avg I(VVDDUS) from='tcyc_1' to='tcyc_2'
.meas tran IAvg_Write_0 avg I(VVDDUS) from='tcyc_2' to='tcyc_3'
.meas tran IAvg_Read_1 avg I(VVDDUS) from='tcyc_3' to='tcyc_4'
.meas tran IAvg_Read_0 avg I(VVDDUS) from='tcyc_4' to='tcyc_5'
.meas IAvg param='(IAvg_Write_1+ IAvg_Write_0+ IAvg_Read_1+ IAvg_Read_0)/4'

.meas tran ILeakT0 avg I(VVDDUS) from='tcyc_2 - 4us' to='tcyc_2 - 2us'
.meas tran ILeakT1 avg I(VVDDUS) from='tcyc_3 - 4us' to='tcyc_3 - 2us'
.meas tran ILeakT2 avg I(VVDDUS) from='tcyc_4 - 4us' to='tcyc_4 - 2us'
.meas tran ILeakT3 avg I(VVDDUS) from='tcyc_5 - 4us' to='tcyc_5 - 2us'
.meas ILeakAvg param='abs(ILeakT0 + ILeakT1 + ILeakT2 + ILeakT3)/4'

.meas tran ILeak0 avg I(VVDDA) from='tcyc_2 - 4us' to='tcyc_2 - 2us'
.meas tran ILeak1 avg I(VVDDA) from='tcyc_3 - 4us' to='tcyc_3 - 2us'
.meas tran ILeak2 avg I(VVDDA) from='tcyc_4 - 4us' to='tcyc_4 - 2us'
.meas tran ILeak3 avg I(VVDDA) from='tcyc_5 - 4us' to='tcyc_5 - 2us'
.meas ILeakAvgArray param='abs(ILeak0 + ILeak1 + ILeak2 + ILeak3)/4'
.meas ILeakAvgPeriphery param='(ILeakAvg - ILeakAvgArray)'

************** Access Time Breakout Timings ****************
.meas tran Tacc trig v(CLK) val='VDD*0.5' td='tcyc_4' rise=1 targ v(dout<127>)
+ val='VDD*0.5' td='tcyc_4' fall=1
.meas AccessTime param='Tacc'

.meas tran TClkRise_2_RWl_Rise_Read trig V(XI0.clk_en) val='0.5*VDD' td='tcyc_4' rise=1
+ targ V(XI0.XI0.net15<0>) val='0.5*VDD' td='tcyc_4' rise=1

.meas tran TRWlRise_2_Dout_Read trig v(XI0.XI0.net15<0>) val='VDD*0.5' td='tcyc_4' rise=1 targ v(dout<127>)
+ val='VDD*0.5' td='tcyc_4' fall=1
************** Write Breakout Timings ****************
.meas tran TClkRise_2_WWl_Rise_Write trig V(XI0.clk_en) val='0.5*VDD' td='tcyc_6' rise=1
+ targ V(XI0.XI3.net14<63>) val='0.5*VDD' td='tcyc_6' rise=1

.meas tran TWWl_Rise_Write when V(XI0.XI3.net14<63>)='0.5*VDD' td='tcyc_6' rise=1

.meas tran TBitFlip_Write when V(XI0.XI3.XI0.XIcell63_127.net062)=V(XI0.XI3.XI0.XIcell63_127.net075) td='tcyc_6' rise=1

.meas tran TWWlRise_2_BitFlip_Write param='(TBitFlip_Write - TWWl_Rise_Write)' 

.meas tran TClkFall2PrechargeRise_Read trig V(XI0.clk_en) val='0.5*VDD' td='tcyc_4' fall=1 targ v(XI0.XI3.net053<127>)
+ val='VDD*0.99' td='tcyc_4' rise=1

.meas tran  Avg_Wr_I_1 avg I(VVDDUS) from='tcyc_1' to='tcyc_2'
.meas tran  Avg_Wr_I_0 avg I(VVDDUS) from='tcyc_2' to='tcyc_3'
.meas tran  Avg_Rd_I_1 avg I(VVDDUS) from='tcyc_3' to='tcyc_4'
.meas tran  Avg_Rd_I_0 avg I(VVDDUS) from='tcyc_4' to='tcyc_5'

.meas Cpd_Wr_1 param='(abs(IAvg_Write_1))*(tcyc_2 - tcyc_1)/VDD'
.meas Cpd_Wr_0 param='(abs(IAvg_Write_0))*(tcyc_3 - tcyc_2)/VDD'
.meas Cpd_Rd_1 param='(abs(IAvg_Read_1))*(tcyc_4 - tcyc_3)/VDD'
.meas Cpd_Rd_0 param='(abs(IAvg_Read_0))*(tcyc_5 - tcyc_4)/VDD'

.meas Energy_Wr_1 param='1/2*Cpd_Wr_1*(VDD^2)'
.meas Energy_Wr_0 param='1/2*Cpd_Wr_0*(VDD^2)'
.meas Energy_Rd_1 param='1/2*Cpd_Rd_1*(VDD^2)'
.meas Energy_Rd_0 param='1/2*Cpd_Rd_0*(VDD^2)'

.tran 1n 45us 
*.tran 1n 210us 
*sweep Num 1 10 
.probe v(*) i(*) level=1 
.probe  v(XI0.*) level=1
.probe  v(XI0.XI0.*) level=1
.probe  v(XI0.XI1.*) level=1
.probe  v(XI0.XI2.*) level=1
.probe  v(XI0.XI3.*) level=1
.probe  v(XI0.XI0.XI1.*) level=1
.probe  v(XI0.XI0.XI2.*) level=1
.probe  v(XI0.XI1.XI1.*) level=1
.probe  v(XI0.XI1.XI2.*) level=1
.probe  v(XI0.XI2.XI1.*) level=1
.probe  v(XI0.XI2.XI2.*) level=1
.probe  v(XI0.XI3.XI1.*) level=1
.probe  v(XI0.XI3.XI2.*) level=1
.probe  v(XI0.XI0.XI0.XIcell63_127.*) level=1
.probe  v(XI0.XI0.XI0.XIcell0_127.*) level=1
.probe  v(XI0.XI0.XI0.XIcell0_0.*) level=1
.probe  v(XI0.XI0.XI0.XIcell63_0.*) level=1
.probe  v(XI0.XI1.XI0.XIcell63_127.*) level=1
.probe  v(XI0.XI1.XI0.XIcell0_127.*) level=1
.probe  v(XI0.XI1.XI0.XIcell0_0.*) level=1
.probe  v(XI0.XI1.XI0.XIcell63_0.*) level=1
.probe  v(XI0.XI2.XI0.XIcell63_127.*) level=1
.probe  v(XI0.XI2.XI0.XIcell0_127.*) level=1
.probe  v(XI0.XI2.XI0.XIcell0_0.*) level=1
.probe  v(XI0.XI2.XI0.XIcell63_0.*) level=1
.probe  v(XI0.XI3.XI0.XIcell63_127.*) level=1
.probe  v(XI0.XI3.XI0.XIcell0_127.*) level=1
.probe  v(XI0.XI3.XI0.XIcell0_0.*) level=1
.probe  v(XI0.XI3.XI0.XIcell63_0.*) level=1
**level=1

.end
